The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed dielectric interlayer dielectrics and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization layers are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the interlayer dielectric layer separating the metallization layers, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization layers is known as “damascene”-type processing. Generally, this process involves forming an opening (or via) in the dielectric interlayer, which will subsequently separate the vertically spaced metallization layers. The via is typically formed using conventional lithographic and etching techniques. After the via is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques. Excess conductive material on the surface of the dielectric interlayer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed “dual damascene” processing, involves the formation of an opening having a lower contact (or via) hole section which communicates with an upper trench section. The opening is then filled with a conductive material to form a conductive plug that electrically contacts the lower metallization layer. As with the previous process, excess conductive material on the surface of the dielectric interlayer is then removed by CMP. An advantage of the dual damascene process is that the conductive plug and the upper metallization layer are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization layers.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization layer and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the inferface with the metallization layer usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI an ULSI semiconductor devices, which require multi-level metallization layers. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known “wet” plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Electroless plating of Cu generally involves the controlled auto-catalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode (comprising the surface(s) to be plated) from an external source (i.e., a power supply) for reducing Cu ions in solution and depositing reduced Cu metal atoms on the plating surface(s). In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
A number of different variations of a damascene process have been employed during semiconductor manufacturing. With reference to FIGS. 1A-1L, a dual damascene process for forming vias and a second metallization layer over a first metallization layer, according to conventional techniques, will be described. This process can be repeated to form multiple metallization levels, i.e., two or more, stacked one on top of another.
In FIG. 1A, a second etch stop layer 12 is deposited over a first metallization layer 10. The second etch stop layer 12 acts as a passivation layer that protects the first metallization layer 10 from oxidation and contamination and prevents diffusion of material from the metallization layer 10 into a subsequently formed dielectric layer. The second etch stop layer 12 also acts as an etch stop during subsequent etching of the dielectric layer. A typical material used as an etch stop is silicon nitride, and approximately 500 angstroms of silicon nitride is typically deposited over the metallization layer 10 to form the second etch stop layer 12. An illustrative process used for depositing silicon nitride is plasma enhanced CVD (PECVD).
In FIG. 1B, a first dielectric layer 14 is deposited over the second etch stop layer 12. The first dielectric layer 14 is generally formed from silicon oxide although other acceptable materials include silicon nitride and organic polymeric materials. Many techniques are capable of forming a dielectric layer 14 formed from silicon oxide, and an illustrative process is PECVD.
FIG. 1C, a first etch stop layer 40 is deposited over the first dielectric layer 14. The first etch stop layer 40 acts as an etch stop during etching of a dielectric layer subsequently formed over the first etch stop layer 40. As with the second etch stop layer 12, a material typically used as an etch stop is silicon nitride, and approximately 500 angstroms of silicon nitride is typically deposited over the first dielectric layer 40 to form the first etch stop layer 40. An illustrative process used for depositing silicon nitride is PECVD.
In FIG. 1D, a second dielectric layer 42 is deposited over the first etch stop layer 40. The second dielectric layer 42 is generally formed from silicon oxide although other acceptable materials include silicon nitride and organic polymeric materials. Many techniques are capable of forming a second dielectric layer 42 formed from silicon oxide, and an illustrative process is PECVD.
In FIG. 1E, the pattern of the vias are formed in the second dielectric layer 42 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 44 over the second dielectric layer 42 and exposing and developing the resist 44 to form the desired pattern of the vias. The first etch, which is highly selective to the material of the second dielectric layer 42, removes the second dielectric layer 42 until the etchant reaches the first etch stop layer 40. The first etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the second dielectric layer 42 directly below the opening in the resist 44.
In FIG. 1F, a second etch, which is highly selective to the material of the first etch stop layer 40, then removes the first etch stop layer 40 until the etchant reaches the first dielectric layer 14. The second etch is also typically an anisotropic etch.
In FIG. 1G, the vias 16 are formed in the first dielectric layer 14 and the trenches 46 of the second metallization layer are formed in the second dielectric layer 42 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 50 over the second dielectric layer 42 and exposing and developing the resist 50 to form the desired pattern of the trenches 46. The third etch, which is highly selective to the material of the first and second dielectric layers 14, 42, removes the first dielectric layer 14 until the etchant reaches the second etch stop layer 12 and removes the second dielectric layer 42 until the etchant reaches the first etch stop layer 40. The third etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the first dielectric layer 14 directly below the opening in the first etch stop layer 40 and the exposed portions of the second dielectric layer 42 directly below the opening in the resist 50. By using an anisotropic etch, the via 16 and the trench 46 can be formed with substantially perpendicular sidewalls.
In FIG. 1H, a fourth etch, which is highly selective to the material of the first and second etch stop layers 40, 12, then removes the second etch stop layer 12 until the etchant reaches the first metallization layer 10 and removes the first etch stop layer 40 until the etchant reaches the first dielectric layer 14. The fourth etch is also typically an anisotropic etch.
In FIG. 1I, the corners 18 of the vias 16 and trenches 46 can be rounded using a reverse sputtering process. The corners 18 of the vias 16 and trenches 46 are rounded to prevent problems of void creation associated with subsequent deposition of the conductive plug and second metallization layer, and if necessary, a barrier layer. The reverse sputtering process can also be used to clean the first metallization layer 10 at the bottom of the via 16. Incomplete etching of the second etch stop layer 12 can leave a portion of the second etch stop layer 12 over the first metallization layer 10, and this material can prevent good ohmic contact between the material of the conductive plug and the material of the first metallization layer 10. Use of the reverse sputtering process, however, can remove any remaining material of the second etch stop layer 12 and any other contaminants on the first metallization layer 10.
In FIG. 1J, an adhesion/barrier material, such as tantalum, titanium, tungsten, tantalum nitride, or titanium nitride, is deposited. The combination of the adhesion and barrier material is collectively referred to as a second diffusion barrier layer 20. The second diffusion barrier layer 20 acts to prevent diffusion into the first and second dielectric layers 14, 42 of the conductive material subsequently deposited into the via 16 and trench 46.
In FIG. 1K, a layer 22 of a conductive material, for example, a Cu or Cu-based alloy, is deposited in the via 16 and trench 46 and over the second dielectric layer 42. A typical process initially involves depositing a “seed” layer on the barrier layer 20 subsequently followed by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the via 16 and trench 46. So as to ensure complete filling of the via 16 and trench 46, the Cu-containing conductive layer 22 is deposited as a blanket (or “overburden”) layer 24 so as to overfill the trench 46 and cover the upper surface 52 of the second dielectric layer 42.
FIG. 1L, the entire excess thickness of the metal overburden layer 24 over the upper surface 52 of the second dielectric layer 42 is removed using a CMP process. A typical CMP process utilizes an alumina (Al2O3)-based slurry, which leaves a conductive plug in the via 16 and a second metallization layer in the trench 46. The second metallization layer has an exposed upper surface 58, which is substantially co-planar with the upper surface 52 of the second dielectric layer 42.
A problem that can be caused by the use of Cu and Cu-based alloys results from Cu having a relatively large diffusion coefficient into silicon oxide and silicon. Once Cu has diffused into these materials, Cu can cause the dielectric strength of these materials to decrease. Thus, if Cu from a plug or metallization layer diffuses into a silicon oxide layer, the layer can become more conductive, and this increase in conductivity can cause short circuits between adjacent conductive regions. These short circuits can therefore result in failure of the semiconductor device. For this reason, Cu conductors are encapsulated by at least one diffusion barrier to prevent diffusion of the Cu into the silicon oxide layer.
The above-described process, however, can still result in copper contamination as a result of the use of reverse physical sputtering to clean the first metallization layer and to round the corners of the trenches and vias. Reverse physical sputtering is a process by which atoms or molecules from the surface of a material are dislocated or removed by the impact energy of gas ions, which are accelerated in an electric field. This process involves the creation of a glow discharge or plasma between an anode and a cathode, such as a semiconductor device, wherein the current therebetween is composed of electron flow to the anode and positive ion flow to the cathode. The ions are created by the ionization of gas molecules, such as argon, existing within the flow discharge region between the anode and cathode. The ionization results from the collision of gas particles with the electron flow from the cathode to the anode. A focused beam of these ions can be directed to a very small point on a semiconductor device and then scanned, raster fashion, over a surface where material is to be removed. As an ion impinges on the semiconductor device surface, momentum is transferred from the ion to the impact surface resulting in the removal of one or more surface atoms.
The problem of copper contamination as a result of reverse sputtering is illustrated in FIG. 2. The reverse physical sputtering process rounds the corners 18 of the vias 16 and trenches 46 as a result of ionized argon impacting the corners 18 and dislodging atoms. As the atoms of argon are impacting the corners 18, the atoms of argon are also impacting all the other exposed surfaces, such as the Cu of the first metallization layer 10. Thus, the impact of the argon atoms onto the first metallization layer 10 also dislodges atoms of Cu, and the dislodged atoms of Cu are free to be redeposited on other surfaces. In particular, the dislodged Cu atoms can be deposited onto the exposed sidewall surfaces 15 of the first and second dielectric layers 14, 42.
Once the Cu is deposited on the first and second dielectric layers 14, 42, the Cu can then diffuse into the first and second layers 14, 42. As previously stated, the diffusion of Cu into a silicon oxide dielectric layer 14, 42 causes detrimental effects that can result in the failure of the semiconductor device. Accordingly, a need exists for an improved method of forming copper plugs and copper metallization that allows for use of reverse sputtering to round corners of vias, so as to minimize the problem of void creation, yet still prevent the dielectric layers from being contaminated with Cu.